Close category search window
 

Advanced dielectric etching with a high density plasma tool: issues and challenges in manufacturing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Cook, J.M. ; Lam Res. Corp., Fremont, CA, USA

Summary form only given, as follows. The requirements for 0.25 μm etch technologies are making successful dielectric etch processing more difficult to realize than ever before. The minute dimensions of the features, coupled with films of widely varying thickness (≈7000 to 20000+Å) result in inherently narrow process windows, wherein the balance between RIE "lag" (ARDE) and selectivity to underlayers (e.g. Si3 N4) that are chemically similar to the film being etched but which have the added property of nonplanarity, and thus higher sputter yield. Maintaining selectivity to impurities, charge-up and particulates require that tools and processes address cleanliness, plasma uniformity and materials to degrees unthinkable until only recently. This paper describes the development of one such tool, a low pressure, inductively coupled, high density plasma system that has addressed a number of the issues arising from these advanced application etches. Among the items and issues discussed will be the underlying principals of operation, the implementation and etch results, especially on contact, self-aligned contact (SAC) and via applications. Issues affecting "manufacturability", their causes and solutions will also be addressed along with some considerations of scaling the system to 300 mm wafer sizes.

Published in:
Advanced Semiconductor Manufacturing Conference and Workshop, 1995. ASMC 95 Proceedings. IEEE/SEMI 1995

Date of Conference: 13-15 Nov 1995

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.