Referenced Items are not available for this document.
Using custom circuitry, a higher level of performance has been achieved for a new implementation of the Scalable Processor Architecture (SPARC). A CY601 processor (integer unit), running at a clock rate of 25-33 MHz, implements the complete set of SPARC instructions in a 0.8- mu m CMOS technology. An overview is given of the processor chip and its interface to the external cache, floating-point unit, and a generic coprocessor.<
Published in:
Compcon Spring '88. Thirty-Third IEEE Computer Society International Conference, Digest of Papers
Date of Conference: Feb. 29 1998-March 3 1988
- Page(s):
- 18 - 20
- Meeting Date :
- 29 Feb 1988-03 Mar 1988
- Print ISBN:
- 0-8186-0828-5
- INSPEC Accession Number:
- 3186046
- Conference Location :
- San Francisco, CA, USA
- Digital Object Identifier :
- 10.1109/CMPCON.1988.4820
- Product Type:
- Conference Publications
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