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Multi-Layer High-K Tunnel Barrier for a Voltage Scaled NAND-Type Flash Cell

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8 Author(s)

Low-voltage program/erase (P/E) operations of a NAND-type flash cell have been demonstrated using a multi-layer tunnel barrier. The concept is to achieve low voltage P/E operations similar to a scaled tunnel barrier without compromising retention by exploiting a multi-layer tunnel oxide consisting of a low-k, high-k and low k material. In this study, barrier engineered tunnel oxides of SiO2-HfOx-SiO2 and SiO2- ZrOx-SiO2 were explored using a Metal-Insulator-Nitride-Oxide- Silicon (MINOS) capacitor with a TiN gate electrode. The device programmed/erased at 16/-22 V for 1 ms and it had a memory window of 6 V. The cell showed less than 2 V charge loss after 27 hours when programmed to a 5 V initial window. The proposed high-K tunnel barrier is a promising alternative for tunnel oxide for sub-35 nm NAND Flash technology.

Published in:

Microelectronics and Electron Devices, 2009. WMED 2009. IEEE Workshop on

Date of Conference:

3-3 April 2009

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