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Today, the design of electrostatic discharge (ESD) protection in semiconductor chips and electronic chips is becoming more challenging task in the automotive industry. Since new ESD pulses are found to be located in high voltage/current and high frequency domain, advanced measurement techniques such as very fast (vf) transmission-line pulse (TLP) system is required to test and verifiy the ESD hardness of chips. This paper presents the design of absorptive rise-time filters for vf- and standard TLP measurement systems for high power applications. To investigate the behavior of ESD protection networks under pulses with different slopes, a series of filters with 200 ps, 500 ps, 1 ns, 2 ns, 5 ns, 10 ns, 20 ns and 50 ns rise-time has been realized and characterized at 800 V and 12.8 kW peak power with 100 ns pulse width on 50 Omega load.