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This paper investigates a computer architecture that provides fault detection in the execution elements, redundancy and error coding in memory storage elements, and incorporates software that allows rollback to a recovery boundary in the executing program when errors do occur. The architecture is intended for use in an environment where any errors encountered would be in the processors current computational instructions. The use of dual-rail logic is proposed for the purpose of providing single-bit error detection in computational units. This approach will be step towards creating a reliable computation environment in space based applications where the environment is quite hostile to computing systems.
Date of Conference: 16-18 July 2008