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High performance Hi-K + metal gate strain enhanced transistors on (110) silicon

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14 Author(s)
Packan, P. ; Logic Technol. Dev., Process Technol. Modeling Intel Corp., Hillsboro, OR ; Cea, S. ; Deshpande, H. ; Ghani, T.
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For the first time, the performance impact of (110) silicon substrates on high-k + metal gate strained 45 nm node NMOS and PMOS devices is presented. Record PMOS drive currents of 1.2 mA/um at 1.0 V and 100 nA/um Ioff are reported. It will be demonstrated that 2D short channel effects strongly mitigate the negative impact of (110) substrates on NMOS performance. Narrow width (110) device performance is shown and compared to (100) for the first time. Device reliability is also reported showing no fundamental issue for (110) substrates.

Published in:

Electron Devices Meeting, 2008. IEDM 2008. IEEE International

Date of Conference:

15-17 Dec. 2008

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