PSEUDEC: implementation of the computation-intensive PARTRAN functionality using a dedicated on-line CORDIC co-processor

This paper describes PSEUDEC, a dedicated co-processor and the rationale behind its design. The final goal of our work is to present a single chip solution with low power consumption for an advanced digital hearing aid based on a parameterized transformation of speech (PARTRAN). Characterization of the constituent parts of the PARTRAN algorithm shows that it is well suited for implementation on a heterogeneous architecture. The design strategy used identifies a subset for implementation on dedicated hardware, with a computational complexity roughly equivalent to the performance of a standard 10 MIPS DSP. The subset of PARTRAN implemented by PSEUDEC performs pseudo-decomposition of a 12th order LPC polynomial. An adapted algorithm displays improved dynamic range compared to the conventional solution for DSPs, calculating the amplitude spectrum rather than the power spectrum. Highly pipelined CORDIC-units optimized for the application replaces complex multiplication, trigonometric operations (for e^jω ) and square root (for |a|=√(a_r²+a_i²)), exploiting the power of CORDIC operations in advanced DSP algorithms. PSEUDEC uses redundant data representation and bit-serial arithmetic, most significant digit first (on-line arithmetic) for efficient implementation of operators and for efficient (inter-operator) communication. The inherent nature of on-line arithmetic and the operators used allows for fast and efficient implementation even when using ordinary standard cells