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A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25 \mu m CMOS

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4 Author(s)
Song-Bok Kim ; Dept. of Integrated Analog Circuits, RWTH Aachen Univ., Aachen ; Stefan Joeres ; Ralf Wunderlich ; Stefan Heinen

Quadrature bandpass SigmaDelta modulators based on polyphase filters are suited for analog-to-digital conversion in GSM/EDGE low-IF receivers. This paper presents a continuous-time quadrature bandpass sigma-delta (SigmaDelta) modulator with a chain of integrators with weighted capacitive feedforward summation (CICFF) topology - which is a desirable solution for implementation in low power applications. A new compensation scheme for the polyphase filter is proposed. The summation of feedforward signals is implemented by weighted capacitors, without the necessity of any additional active components. The effectiveness of the proposed architecture is proved on a test chip which was designed in a standard 0.25 mum CMOS technology. The designed SigmaDelta modulator has a power consumption of 2.7 mW at 1.8 V supply voltage, a dynamic range of 90.3 dB and a peak SNDR of 86.8 dB. The chip area is 0.5 times 1.4 mm2 including pads.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:44 ,  Issue: 3 )