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Summary form only only given, as follows. Modern photolithographic technology offers the capability of fabricating MOSFET devices of micron dimensions and less. It is by no means obvious that such small devices can be designed with suitable electrical characteristics for LSI switching applications. In this talk we will describe short-channel devices (Leff ~ l μ) designed by scaling down larger devices with desirable electrical characteristics. Lateral and vertical dimensions, doping level, and operating voltages and currents are scaled in a self-consistent fashion. In this way small devices have been fabricated without the usual deleterious effects associated with short channels. The measured characteristics of these short-channel devices and the larger devices from which they were scaled will be compared. The scaling procedure helps to better understand the limitations of miniaturization of MOS devices. Significant problems are encountered when operating voltages become comparable to the band gap which cannot be scaled within the silicon technology. The subthreshold characteristic of the device then becomes an important consideration. [This reprint (and two more from 1973 and 1974) show the difference between conference and journal reporting in the 1970s. When the concept of scaling first saw the light of day at IEDM in 1972, only an abstract remained as an archive report. By 1973, the IEDM Digest provided a broader overview of Dennard's report. Dennard's 1974 explanation of scaling turned out to be the most cited article in the 51 year history of the JSSC, close to 700 times, according to the last count in 2005 by the independent citation report firm, Thomson ISI.]
Note: Reprinted from Technical Digest. International Electron Devices Meeting, IEEE, 1972, pp. 168-170.