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The Optimal window-BGA Design for High-Speed SDRAM

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5 Author(s)
Chih-Yi Huang ; Electrical Laboratory, Advanced Semiconductor Engineering, Inc., 26, Chin 3rd Rd., 811, Nantze Export Processing Zone, Kaohsiung, Taiwan, R.O.C, Tel: +886-7-361-7131 Ext. 85291, Fax: +886-7-3613094, E-mail: Joey ; Hung-Hsiang Cheng ; Chen-Chao Wang ; Ya-Wen Huang
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The high performance window-BGA for a high speed Synchronous Dynamic Random Access Memory (SDRAM) has been designed. In this paper, power distribution system (PDS) design on IC package is discussed and studied. A appropriate PDS design will provide not only the stable power supply but also the superior current return path for signal channels. The simulation approach will cover complete Signal Integrity (SI) and Power Integrity (PI) analysis to quantify the electrical performance. The parasitical parameters of IC package including resistance, inductance and capacitance are extracted to check low frequency performance, and S-parameters are performed to observe the broad bandwidth response to ensure sufficient low transmission loss through entire operation frequency range. The PDS behavior in both frequency and time domain are characterized to make sure the PDS performance. Finally, eye diagram are analyzed to inspect overall electrical performance.

Published in:

2008 3rd International Microsystems, Packaging, Assembly & Circuits Technology Conference

Date of Conference:

22-24 Oct. 2008