By Topic

Erase and Retention Improvements in Charge Trap Flash Through Engineered Charge Storage Layer

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

10 Author(s)
N. Goel ; FEP Group at SEMATECH, Austin, TX ; D. C. Gilmer ; H. Park ; V. Diaz
more authors

The simultaneous improvement in the erase and retention characteristics in a TANOS (TaN-Al2O3-Si3N4-SiO2-Si) flash memory transistor by utilizing the band-engineered and compositionally graded SiNx trap layer is demonstrated. With the process optimizations, a > 4V memory window and excellent 150 degC 24-h retention (0.1-0.5 V charge loss) for a programmed DeltaVt = 4V with respect to the initial state are obtained. The band-engineered SiNx charge storage layer enables flash scaling beyond the floating-gate technology with a promise for improved erase speed, retention, lower supply voltages, and multilevel cell applications.

Published in:

IEEE Electron Device Letters  (Volume:30 ,  Issue: 3 )