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High-Throughput Layered LDPC Decoding Architecture

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3 Author(s)
Zhiqiang Cui ; Oregon State Univ., Corvallis, OR ; Zhongfeng Wang ; Youjian Liu

This paper presents a high-throughput decoder architecture for generic quasi-cyclic low-density parity-check (QC-LDPC) codes. Various optimizations are employed to increase the clock speed. A row permutation scheme is proposed to significantly simplify the implementation of the shuffle network in LDPC decoder. An approximate layered decoding approach is explored to reduce the critical path of the layered LDPC decoder. The computation core is further optimized to reduce the computation delay. It is estimated that 4.7 Gb/s decoding throughput can be achieved at 15 iterations using the current technology.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:17 ,  Issue: 4 )