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Through Silicon Vias Technology for CMOS Image Sensors Packaging: Presentation of Technology and Electrical Results

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12 Author(s)
D. Henry ; CEA-LETI, MINATEC, 17 rue des Martyrs, 38054 Grenoble Cedex 9 ¿ France, ; J. Charbonnier ; P. Chausse ; F. Jacquet
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In this paper a low temperature 'via-last' technology will be presented. This technology has been especially developed for CMOS image sensors wafer level packaging. In the first part of this paper, the design of the TSV will be presented and a first approach of a design rule definition for TSV will be introduced. The alignment strategy will be also presented, and specific patterns to succeed front side to back side alignment will be described. In a second part the steps of the Through Silicon Vias (TSV) technology will be briefly presented: glass wafer carrier bonding onto the silicon substrate, silicon thinning and backside technology including specific steps like double side lithography, silicon deep etching, silicon side wall insulation, vias metallization and final bumping. Then, morphological characterizations of the via-last technology will be presented and discussed. Finally, electrical characterization including vias continuity, single via electrical resistance, insulation layer leakage current and breakdown voltage have been measured and will be discussed. A picture obtained with the TSV CMOS Image Sensor (TSV CIS) will be also shown.

Published in:

Electronics Packaging Technology Conference, 2008. EPTC 2008. 10th

Date of Conference:

9-12 Dec. 2008