Referenced Items are not available for this document.
The latest packaging trend of three dimensional system in package (3D-SiP), based either on direct 3D silicon IC stacking or on the use of silicon or organic interposers, is placed in the context of the historical trend toward smaller, faster, and cheaper electronic systems. It can be shown that virtually all packaging advances have been directed toward the reduction of total system interconnect length, and the reduction of superfluous material not required to perform electronic functions. Examples are presented from the days of vacuum tube systems to the present 3D silicon approaches. Various technologies being developed for 3D-SiP are described. Though these approaches differ in technical details, they are all attempting to continue the 50+ year tread of electronics miniaturization through reducing material volume and interconnect length.
Published in:
VLSI Packaging Workshop of Japan, 2008. VPWJ 2008. IEEE 9th
Date of Conference: 1-2 Dec. 2008
- Page(s):
- 3 - 6
- Print ISBN:
- 978-1-4244-3498-5
- INSPEC Accession Number:
- 10400980
- Conference Location :
- Kyoto
- Digital Object Identifier :
- 10.1109/VPWJ.2008.4762187
- Product Type:
- Conference Publications
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