An architecture for the implementation of a parallel marker propagation system

An architecture is proposed which allows the construction of massively parallel (i.e. multibillion node, multi-trillion linked) marker propagation systems. The nodes used in this architecture allow the best intersection of markers to be found by comparing the contents of the intersection register with the descending values on the control word bus. The physical implementation consists of a silicon structure which is composed of 20000 functional planes of silicon-based circuitry, interconnected by 5 billion vertical interconnecting wires. Any node can be linked directly with any other node.<
>