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NAP (no ALU processor): the great communicator

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2 Author(s)
Fried, J. ; MIT Lab. for Comput. Sci., Cambridge, MA, USA ; Kuszmaul, B.C.

A processor chip for use in massively parallel computer called the no ALU (arithmetic and logic unit) processor (NAP) is described. This processor is an experimental design incorporating several architectural features which make it simple to program, general-purpose, and efficient. The arithmetic functions normally performed by an ALU are instead performed by table lookups into memory. In addition, a very flexible programming model is provided, which supports indirect addressing and multiple concurrent instructions while operating in a single-instruction multiple-data (SIMD) or multiple-SIMD (MSIMD) mode. The instruction set architecture of the NAP and the processor design and the implementation of the NAP chip are discussed. The NAP is evaluated, and the lessons learned from this project are summarized

Published in:

Frontiers of Massively Parallel Computation, 1988. Proceedings., 2nd Symposium on the Frontiers of

Date of Conference:

10-12 Oct 1988