For the first time, internal spacers have been introduced in multichannel CMOSFET (MCFET) structures, featuring a decrease of the intrinsic CV/I delay by 39%. The process steps introduced for this new MCFET technological option are studied and optimized in order to achieve excellent ION/IOFF characteristics (NMOS: 2.33 mA/mum at 27 pA/mum and PMOS: 1.52 mA/mum at 38 pA/mum). A gate capacitance C gg reduction of 32% is measured, thanks to S-parameter extraction. Moreover, a significant improvement of the analogical figure of merit is measured compared with optimized fully depleted silicon-on-insulator planar reference; the voltage gain A VI( = gm/g ds) is improved by 92%.
Published in:
Electron Device Letters, IEEE
(Volume:30
,
Issue:
2
)
Date of Publication:
Feb. 2009
- Page(s):
-
148
-
151
- ISSN :
-
0741-3106
- INSPEC Accession Number:
-
10467342
- Digital Object Identifier :
-
10.1109/LED.2008.2009008
- Product Type:
-
Journals & Magazines
- Date of Publication :
-
09 January 2009
- Date of Current Version :
-
23 January 2009
- Issue Date :
-
Feb. 2009
- Sponsored by :
-
IEEE Electron Devices Society