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Several hash functions have been presented to replace previous standard hash families SHA-1 and SHA-2. Besides resistance to cryptanalysis, new candidates should feature a good flexibility to be implemented in hardware. This paper investigates the VLSI design of three emerging hash algorithms. The functions RADIOGATUN, MAME, and LAKE have been implemented and synthesized for ASIC and FPGA target devices. The achieved results point out that the fastest circuit, exceeding 600 MHz in a 0.18 Â¿m CMOS technology and 300 MHz in a Xilinx Virtex-4 FPGA, is RADIOGATUN, while the 9,1 k gate equivalents (GE) implementation of MAME demonstrates the suitability of the algorithm for applications under limited resources.