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Partial Reconfiguration Applied in an On-line Evolvable Pattern Recognition System

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3 Author(s)
Jim Torresen ; Department of Informatics, University of Oslo P.O. Box 1080 Blindern, N-0316 Oslo, Norway, E-mail: jimtoer@ifi.uio.no, Web: http://www.ifi.uio.no/~jimtoer ; Geir Aarstad Senland ; Kyrre Glette

One of the main challenges with autonomous adaptable systems is the lack of hardware flexibility. However, reconfigurable logic is a promising technology for run-time adaptable systems ¿ often called reconfigurable computing. The paper outlines how reconfiguration can be applied at run-time for an on-line evolvable system to improve flexibility in the hardware. The challenge of the latter is to include flexibility without resynthesis and avoid having a too large logic gate overhead. An architecture based on system-on-chip and partial reconfiguration is presented in the paper. Results from implementation show that reconfiguration can be undertaken in a few milliseconds for one category detection module of our classification system.

Published in:

NORCHIP, 2008.

Date of Conference:

16-17 Nov. 2008