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A Subthreshold SCL Based Pipelined Encoder for Ultra-Low Power 8-bit Folding/Interpolating ADC

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3 Author(s)
Beikahmadi, M. ; Microelectron. Syst. Lab., Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland ; Tajalli, A. ; Leblebici, Y.

The subthreshold MOS source-coupled logic (STSCL) technique is of great interest for designing ultra low power circuits. In this paper we discuss the design of a pipelined encoder for an 8-bit folding and interpolating (F&I) analog-to-digital (ADC) data converter using this technique. The encoder is designed and characterized in a conventional 0.18 ¿m CMOS technology, and it is capable of operating over a wide frequency range (10 kHz-50 MHz) without the need of resizing the transistors or scaling the voltage levels. The speed and power consumption of the encoder are proportional to the bias currents of the gates. The supply voltage of the circuit can be as low as 350 mV.

Published in:

NORCHIP, 2008.

Date of Conference:

16-17 Nov. 2008