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A 65 nm 2-Billion Transistor Quad-Core Itanium Processor

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12 Author(s)
Stackhouse, B. ; Intel Corp., Fort Collins, CO ; Bhimji, S. ; Bostak, C. ; Bradley, D.
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This paper describes an Itanium processor implemented in 65 nm process with 8 layers of Cu interconnect. The 21.5 mm by 32.5 mm die has 2.05B transistors. The processor has four dual-threaded cores, 30 MB of cache, and a system interface that operates at 2.4 GHz at 105degC . High speed serial interconnects allow for peak processor-to-processor bandwidth of 96 GB/s and peak memory bandwidth of 34 GB/s.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:44 ,  Issue: 1 )

Date of Publication:

Jan. 2009

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