Designing SONET/ATM layer processing ASICs using embedded approach

Embedded processor based system on a chip device for SONET/ATM applications can enhance the flexibility of the devices to accommodate a wide range of applications and variations in standards. Due to high data rate requirements combined with real-time constraints limit the capabilities of uniprocessor architecture. This paper presents a multiprocessor architecture for designing SONET/ATM ASICs using embedded approach. All of the processing units in the multiprocessor core share a common code or instruction memory to achieve area efficiency. A central sequencer is used to service the processors to achieve control efficiency. The proposed processing unit is focused on two important factors essential for embedded architecture on ASICs-high level instruction with single cycle execution and configurable IO port controller. Functional mapping of the processing units is achieved through data flow analysis. Design approach and potential application of the proposed architecture are illustrated