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Finding Speedup in Parallel Processors

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4 Author(s)
Flynn, M. ; Stanford Univ., Stanford, CA, USA ; Dimond, R. ; Mencer, O. ; Pell, O.

While recently the focus of architects and programmers has been on multi core, the alternative of processor node plus array oriented accelerator has some significant advantages especially in compute intensive static applications. We propose an acceleration methodology based on FPGA arrays (but, in principle it could be GPU or Cell based). The methodology uses a comprehensive application analysis supported by high performance FPGA hardware. The analysis provides a dataflow graph of the application which is replicated in SIMD for multiple data strips until limited by the pin bandwidth, then pipelined (MISD) until circuit limited. An oil exploration application shows the possibility of speedup of over 300x over an Intel Xeon.

Published in:

Parallel and Distributed Computing, 2008. ISPDC '08. International Symposium on

Date of Conference:

1-5 July 2008

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