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Designing a new encryption method for optimum parallel performance

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2 Author(s)
Posch, K.C. ; Inst. for Applied Inf. Process. & Commun., Graz Univ. of Technol., Austria ; Posch, K.C.

This paper describes the design process from algorithm design to the chip level for a parallel implementation of a modified version of the RSA encryption method. The final system consists of several dozens of custom chips computing module exponentiation based on residue number system coding. Emphasis is put on the hierarchical design view, its benefits and ifs shortcomings

Published in:

Algorithms and Architectures for Parallel Processing, 1995. ICAPP 95. IEEE First ICA/sup 3/PP., IEEE First International Conference on  (Volume:2 )

Date of Conference:

19-21 Apr 1995