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A Systematic Approach to Memory Test Time Reduction

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4 Author(s)
Jen-Chieh Yeh ; Industrial Technology Research Institute ; Shuo-Fen Kuo ; Chao-Hsun Chen ; Cheng-Wen Wu

This article describes a method for reducing overall memory test time without sacrificing fault coverage. Key to this method is a test time reduction tool that helps remove redundant test items from the test flow, merge existing test patterns, and develop efficient new test patterns.

Published in:

IEEE Design & Test of Computers  (Volume:25 ,  Issue: 6 )