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Defect Tolerance for Nanoscale Crossbar-Based Devices

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2 Author(s)
Tehranipoor, M. ; Univ. of Connecticut, Storrs, CT ; Rad, R.M.P.

The need for defect maps and per-chip placement and routing limits the efficiency of test and defect tolerance techniques in nanoscale crossbar-based devices. The authors propose a method using two simulation programs that circumvents these difficulties to find fault-free implementations of logic functions on defective crossbars.

Published in:

Design & Test of Computers, IEEE  (Volume:25 ,  Issue: 6 )