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Hardware Efficient Low-Latency Architecture for High Throughput Rate Viterbi Decoders

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2 Author(s)
Chao Cheng ; Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN ; Keshab K. Parhi

By optimizing the number of look-ahead steps of the first layer of the previous low-latency architectures for M-step look-ahead high-throughput rate Viterbi decoders, this paper improves the hardware efficiency by large percentage with slight increase or even further decrease of the latency for the add-compare-select (ACS) computation. This is true especially when the encoder constraint length (K) is large. For example, when K = 7 and M varies from 21 to 84, 20.83% to 41.27% of the hardware cost in previous low latency Viterbi method can be saved with only up to 12% increase or 4% decrease of the latency of the conventional M-step look-ahead Viterbi decoder. The proposed architecture also relaxes the constraint on the look-ahead level M to be a multiple of K as was needed in the previous work. For example, when K = 7 and M (indivisible by K) varies from 40 to 80, 60.27% to 69.3% latency of conventional M-step look ahead Viterbi architecture can be reduced at the expense of 148.62% to 320.20% extra hardware complexity.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:55 ,  Issue: 12 )