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A comprehensive modeling methodology is presented for the investigation of on-chip noise generation and coupling due to power switching. The backbone of the methodology is an electromagnetic model for the on-chip portion of the power grid. This allows for the impact of the displacement current density and, hence, electromagnetic retardation, to be taken into account in the accurate modeling of the power grid behavior at picosecond switching speeds. In this manner, and through the interfacing of this model with an electromagnetic model for the package portion of the power grid, which is described in terms of a multiport rational matrix transfer function, the impact of package-chip electrical interactions on switching noise can be modeled with electromagnetic accuracy. The electromagnetic model for the power grid is complemented by a resistance-capacitance model for the semiconductor substrate, which is capable of modeling local substrate induced noise coupling between neighboring circuits. Finally, distributed resistance, inductance, capacitance and conductance circuits for signal wires are extracted and used to provide for a transmission line-based modeling of crosstalk and power grid induced signal degradation. Transient simulations using the proposed comprehensive model are carried out using a hybrid time-domain integration scheme which combines a SPICE-like engine for the analysis of all circuit netlists and the nonlinear drivers incorporated in the model with a numerical integration algorithm suitable for the expedient update of the state variables in the discrete electromagnetic model for the power grid.