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Nanopower Subthreshold MCML in Submicrometer CMOS Technology

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3 Author(s)
Francesco Cannillo ; Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK ; Christofer Toumazou ; Tor Sverre Lande

This paper presents subthreshold MOS current-mode logic (MCML) circuits implemented in a commercial 0.25-mum CMOS technology. We propose the adoption of bulk-drain-connected pMOS transistors as loads for subthreshold MCML gates. The b-d connection extends the linear operating range of the load, thus increasing the output logic swing of the subthreshold MCML gate. Theoretical and measured results are presented for an MCML inverter and a ten-stage ring oscillator operating at supply voltages below the threshold-voltage value, with power consumption on the order of nanowatts. At a 300-mV supply, the oscillator works at a frequency of 638 Hz with a total power consumption of 345 pW.

Published in:

IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:56 ,  Issue: 8 )