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A charge-pump phase-locked loop with a switched capacitor loop filter and kilohertz order reference with 0.35 mum high-voltage CMOS process is presented. The PLL is designed for a reference frequency range from 3 kHz to 10 kHz in temperature range from -40degC to +85degC and with 2.5 to 3.6 V supply. Simulations showed that the current consumption of the PLL is 7.3 muA with the 4 kHz reference frequency and 3.0 V nominal supply. Derivation of the equivalent resistance and the linear model of the PLL with both an RC- and SC-type loop filter is presented and compared between each other. It is shown that significant area improvement can be achieved with the SC-filter.