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A hardware implementation of a binary neural image processor

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3 Author(s)
Kennedy, J.V. ; York Univ., UK ; Austin, J. ; Cass, B.

The paper presents the work that has resulted in the sum and threshhold (SAT) processor; a dedicated hardware implementation of a binary neural image processor. The SAT processor is aimed specifically at supporting the ADAM algorithm and is currently being integrated into a new version of the C-NNAP parallel image processor. The SAT processor performs binary matrix multiplications, a task that is computationally complex for a CPU with a standard instruction set. It can perform the matrix multiplication and thresholding between 100 and 200 times faster than the DSP32C that uses an in-house produced dedicated coprocessor. This speed-up will allow the SAT to process images of up to 220×220 pixels at 25-Hz frame rates

Published in:

Image Processing and its Applications, 1995., Fifth International Conference on

Date of Conference:

4-6 Jul 1995