By Topic

A hardware implementation of a binary neural image processor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $33
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
J. V. Kennedy ; York Univ., UK ; J. Austin ; B. Cass

The paper presents the work that has resulted in the sum and threshhold (SAT) processor; a dedicated hardware implementation of a binary neural image processor. The SAT processor is aimed specifically at supporting the ADAM algorithm and is currently being integrated into a new version of the C-NNAP parallel image processor. The SAT processor performs binary matrix multiplications, a task that is computationally complex for a CPU with a standard instruction set. It can perform the matrix multiplication and thresholding between 100 and 200 times faster than the DSP32C that uses an in-house produced dedicated coprocessor. This speed-up will allow the SAT to process images of up to 220×220 pixels at 25-Hz frame rates

Published in:

Image Processing and its Applications, 1995., Fifth International Conference on

Date of Conference:

4-6 Jul 1995