Referenced Items are not available for this document.
Before verifying the functionality of SoCs, designers must ensure the correctness of the pin-accurate interfaces of up to hundreds of integrated IP blocks. This article presents a new connection model and a corresponding error model for pin-accurate port connections, along with an algorithm for generating the minimum pattern set, a methodology for diagnosing errors, and a port connection verification flow.
Published in:
Design & Test of Computers, IEEE
(Volume:25
,
Issue:
5
)
Date of Publication: Sept.-Oct. 2008
- Page(s):
- 478 - 486
- ISSN :
- 0740-7475
- INSPEC Accession Number:
- 11409850
- Digital Object Identifier :
- 10.1109/MDT.2008.149
- Date of Current Version :
- 10 October 2008
- Issue Date :
- Sept.-Oct. 2008
- Sponsored by :
- IEEE Council on Electronic Design and Automation
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