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Signal Integrity Enhancement in Digital Circuits

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8 Author(s)

This article proposes a new methodology for enhancing SoC signal integrity without degrading performance in the presence of power-ground voltage transients. The underlying principle is the dynamic adaptation of the clock duty cycle to propagation delay variation along disturbed logic paths. This methodology makes digital circuits more robust to power line fluctuations while maintaining the at-speed clock rate.

Published in:

IEEE Design & Test of Computers  (Volume:25 ,  Issue: 5 )