By Topic

Radix-4 modules for high-performance bit-serial computation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Smith, S.G. ; University of Edinburgh, Department of Electrical Engineering, Edinburgh, UK ; Denyer, P.B.

We describe a technique to double the throughput of bit-serial computational networks, while retaining the many advantages associated with this architectural approach. In essence this technique relies on a 2-wire radix-4 representation of serial data: a step towards bit parallelism. As the cost of data storage associated with bit-serial architectures is not increased by this technique, it has a favourable effect on overall area-time product. Novel use of the well-known modified-Booth recoding multiplication algorithm results in further area savings. A set of functional building blocks and interfacing conventions is outlined, forming the basis of a cell library for use in a silicon compilation environment.

Published in:

Computers and Digital Techniques, IEE Proceedings E  (Volume:134 ,  Issue: 6 )