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sFPGA — A scalable switch based FPGA architecture and design methodology

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3 Author(s)
Shakith Fernando ; Department of Electrical and Computer Engineering, National University of Singapore, Singapore ; Xiaolei Chen ; Yajun Ha

The poor scalability of current mesh-based FPGA interconnection networks is impeding our attempts to build next-generation FPGA of larger logic capacity. A few alternative interconnection network architectures have been proposed for future FPGAs, but they still have several design challenges that need to be addressed. In this paper, we propose sFPGA, a scalable FPGA architecture, which is a hybrid between hierarchical interconnection and network-on-chip. The logic resources in sFPGA are organized into an array of logic tiles. The tiles are connected by a hierarchical network of switches, which route data packets over the network. In addition, we have proposed a design flow for sFPGA which integrates current design flows seamlessly. By doing a case study in our emulation prototype, we have validated our sFPGA design flow.

Published in:

2008 International Conference on Field Programmable Logic and Applications

Date of Conference:

8-10 Sept. 2008