Design Methodology for Electron-Trap Memory Cells

In order to further reduce the feature size of semiconductor devices, the field of single-electronics has come of age. Single electron tunneling (SET) technology uses a single or few electrons to implement various analog and digital applications. Memory design is such a typical example. In this paper, we present a design methodology by discussing the parameter selection and reliability analysis for SET-based electron-trap memory cells. It is shown that the parameter selection is important for correct logic operation of these memory cells as well as their reliability improvement. All the results are verified by the SIMON simulator.