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The package on package (POP) stacking is getting more and more popular for system in package (SIP) applications. But during the assembly process, the POP had encountered the challenge of packages stacking yield loss, especially when top package and bottom package stacking. The key factors are the mount height of top package, the mold cap of bottom package, and the metallized ball land on the top surface of bottom package. JEDEC JC-11 has defined the rules of two packages stacking. However, the fine pitch package stacking application will meet the process capability limitation, including thinner mold cap, wafer thinning and the lowest wire bond loop height challenges. The POP used the top gate mold chase for the bottom package to expose the metallized ball land on the top side of package which is a dedicated molding tooling. Also, some process are used for solving yield loss issues such as a POP with interposer between top package and bottom package, or a bottom package with pre-mounted the solder ball on chip side ready for top package to attach. Those are customized tooling and not a prevailing tooling that increases the developing cost and timing. To resolve the stacking process yield loss issue, a MAPPOP solution had been revealed for eliminating the limitation between the top and bottom package stacking. The assembly process of mold array package (MAP) for fine pitch BGA has been implemented for MAPPOP applications. In the paper, the package design rules, and assembly process of exposed metallized ball land on the top surface of bottom package had been discussed. Finally the warpage performance and the packaging level reliability had also been discussed and analyzed.
Date of Conference: 28-31 July 2008