This paper investigates the behaviors of multi-island structure as an alternative redundancy scheme for single-electron tunneling (SET) based digital circuits. In particular, we focus on an SET logic gate (2-input NAND gate) to explore the role of this structure in improving the immunity against random background charges. Also discussed are the parameter selection with multi-island structure, and the difference between this structure and the existing redundancy strategy. Experiments using SIMON simulator show the advantages of the proposed structure.
Published in:
Nanotechnology, 2007. IEEE-NANO 2007. 7th IEEE Conference on
Date of Conference: 2-5 Aug. 2007