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A laminate design technology of metal gates is proposed to improve FET characteristics regardless of EOT and gate dielectric material. The laminated metal gate structures are basically composed of low-Rs(sheet resistance) metal/ WF(work-function)-lowering layer/ WFM(WF determining metal). A thin WFM (~2 nm) laminated by the Si-based WF-lowering layer such as poly-Si or TaSiN brings an additional benefit of dramatic improvements in mobility and PBTI in nFETs. A thick WFM (~10 nm) suppresses the WF-lowering in pFETs. The concept of the laminate design is indispensable for improving the performance in CMOSFETs.