TSNWFET for SRAM cell application: Performance variation and process dependency

I_ON is increased about 25 % with the width/height (W/H) of 12/24 nm nanowire (NW) in comparison with the W/H of 12/12 nm at V_G-V_TH = 1 V. With these results, we have successfully fabricated NW SRAM arrays with the W/H of 5/15 nm and LG of 40 nm for the first time. Static noise margin (SNM) of 325 mV is achieved at V_D = 1 V. NW height and gate oxide thickness dependency of n-ch twin silicon nanowire MOSFET (TSNWFET) on device variations is investigated. Line edge roughness and size variation are more critical than random dopant fluctuation in TSNWFET.