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Novel and cost-efficient single metallic silicide integration solution with dual Schottky-barrier achieved by aluminum inter-diffusion for FinFET CMOS technology with enhanced performance

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13 Author(s)
Rinus Tek-Po Lee ; Silicon Nano Device Lab., Dept. of Electrical and Computer Engineering, National University of Singapore, 117576, Singapore ; Alvin Tian-Yi Koh ; Wei-Wei Fang ; Kian-Ming Tan
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We have developed a novel and cost-efficient silicide integration solution to achieve a hole barrier height of 215 meV and electron barrier height of 665 meV simultaneously with a single metallic silicide based on aluminum inter-diffusion. It is proposed that aluminum diffuses into PtSi and forms an alloy, which lowers the electron barrier height of PtSi due to a change in the intrinsic PtSi workfunction. Additionally, we have integrated platinum germanosilicide with an ultra-low hole barrier height of 215 meV in P-FinFETs to provide a 21% enhancement in drive current performance, which is attributed to the 20% reduction in series resistance. We have also ascertained the compatibility of PtSiGe with laser thermal annealing for further performance enhancement.

Published in:

2008 Symposium on VLSI Technology

Date of Conference:

17-19 June 2008