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A 40Gb/s low-power analog equalizer in 0.13μm CMOS technology

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3 Author(s)
Jian-Hao Lu ; Graduate Institute of Electronics Engineering & Department of Electrical Engineering, National Taiwan University, Taipei 10617, China ; Ke-Hou Chen ; Shen-Iuan Liu

A 40 Gb/s low-power analog equalizer has been realized in 0.13 mum CMOS technology. To achieve a peaking gain of 10 dB at 20 GHz and low power dissipation, an inductive feedback stage is proposed. This inductive feedback stage consumes 3.6 mW from a 1.2 V supply and the whole equalizer consumes 14.4 mW. The chip occupies 0.57 times 0.44 mm2. For a 40 Gb/s PRBS of 27-1, the measured BER is less than 10-12 and the measured maximum peak-to-peak jitter is 12.6 ps.

Published in:

2008 IEEE Symposium on VLSI Circuits

Date of Conference:

18-20 June 2008