By Topic

Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)

Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering clock energy and removing datapath metastability. Error-recovery circuits replay failing instructions at lower clock frequency to guarantee correct functionality. Relative to conventional circuits, silicon measurements indicate that resilient circuits enable either 25 to 32% throughput gain at equal VCC or at least 17% VCC reduction at equal throughput, resulting in 31 to 37% total power reduction.

Published in:

Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on

Date of Conference:

2-4 June 2008