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Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance

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8 Author(s)
Keith A. Bowman ; Intel Corporation, Hillsboro, OR, USA ; James W. Tschanz ; Nam Sung Kim ; Janice C. Lee
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Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering clock energy and removing datapath metastability. Error-recovery circuits replay failing instructions at lower clock frequency to guarantee correct functionality. Relative to conventional circuits, silicon measurements indicate that resilient circuits enable either 25 to 32% throughput gain at equal VCC or at least 17% VCC reduction at equal throughput, resulting in 31 to 37% total power reduction.

Published in:

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial

Date of Conference:

2-4 June 2008