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FPGA Implementation of an Asynchronous Processor with Both Online and Offline Testing Capabilities

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4 Author(s)
Minas, N. ; Newcastle Univ., Newcastle upon Tyne ; Marshall, M. ; Russell, G. ; Yakovlev, A.

Due to aggressive technology scaling VLSI circuits have become more susceptible to transient errors. The associated reduction in supply voltages has decreased noise margins, causing system reliability to be reduced increasingly at a time when electronic systems are being used in ldquosafety criticalrdquo applications. Clock distribution issues as well as the demands for low power circuits have exposed the limitations of the synchronous design paradigm. Asynchronous circuits appear to be an alternative, offering low power and low EMI. However the design complexity involved, the lack of CAD tools and the issues of testability have made this class of circuits unfavourable with digital designers. In this paper an asynchronous RISC based processor is introduced with both online and offline testing capabilities, thus offering a solution to the testability problem. The processor uses a Concurrent Error Detection (CED) scheme to identify transient errors. Detection of hard errors is done using an embedded asynchronous functional tester, where the asynchronous Device Under Test (DUT) is able to control the tester rather than being dictated by the clock in synchronous ATE. The processor and the equivalent test circuitry have been implemented on a Xilinx Virtex2 1000 FPGA.

Published in:

Asynchronous Circuits and Systems, 2008. ASYNC '08. 14th IEEE International Symposium on

Date of Conference:

7-10 April 2008