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A Mature Methodology for Implementing Multi-Valued Logic in Silicon

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2 Author(s)
Nodine, M.H. ; Intrinsity, Inc., Austin, TX ; Files, C.M.

This paper gives an overview of methods proposed for implementing multi-valued logic in CMOS and then describes Intrinsity's patented Fast14reg Technology as a mature methodology for silicon implementation of multi-valued logic. To the authors' knowledge, no previous method of implementing multi-valued logic has been demonstrated with a design of the complexity of a microprocessor core. Fast14 Technology is based upon three fundamental characteristics including the use of (1) footed NMOS transistor domino logic, (2) multi-phased overlapping clocks, and (3) 1-of-N encoding of MVL signals. To provide additional opportunities for power optimization, the concepts of null value and mutex properties are introduced, presenting additional challenges for MVL representation and synthesis.

Published in:

Multiple Valued Logic, 2008. ISMVL 2008. 38th International Symposium on

Date of Conference:

22-24 May 2008