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An analog-to-digital converter (ADC) architecture that simultaneously converts two channels is presented. The ADC is intended for use in portable broadband radio receivers that employ in-phase (I) and quadrature (Q) signal paths and will provide an optimal combination of low cost, low power, and high performance. The architecture is pipeline based and employs two separate first stages followed by shared stages for the remainder of the pipeline. A clock generation system for generating all of the required nonoverlapping clock phases is also presented. A prototype ADC with 10 bit resolution and a 40 MHz sample rate that employs the proposed ADC architecture has been fabricated using a 90 nm all-digital CMOS process and occupies an area of 1.727 mm2 for a per-channel area of 0.864 mm2. The measured performance for the two-channel ADC is a peak signal-to-noise ratio (SNR) and signal-to-noise-plus-distortion ratio (SNDR) of 58.4 dB and 56.5 dB, respectively, and differential nonlinearity (DNL) and integral nonlinearity (INL) of -0.48/+0.58 LSB and plusmn1 LSB, respectively, with a power dissipation of 50 mW (including analog, digital, and clock generator power) from a 2.5 V supply (1.2 V for the digital section), giving a per-channel power dissipation of 25 mW.
Date of Publication: June 2008