Implementation of an asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array

In this paper we present an implementation of an asynchronous cellular processor array that facilitates binary trigger-wave propagations, extensively used in various image processing algorithms. The circuit operates in a continuous-time mode, achieving high operational performance and low power consumption. A 24 times 60 proof-of-concept array integrated circuit has been fabricated in a 0.35 mum 3-metal CMOS process and tested. Occupying only 16 times 8 mum² the binary wave-propagation cell is used as a coprocessor in a general-purpose processor-per-pixel array that is designed for focal-plane image processing. The results of global operations such as object reconstruction and hole filling are presented.