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A low-power CMOS analog voltage buffer using compact adaptive biasing

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4 Author(s)
Sawigun, C. ; Dept. of Electron. Eng., Mahanakorn Univ. of Technol., Bangkok ; Mahattanakul, J. ; Demosthenous, A. ; Pal, D.

A CMOS analog buffer with high output drivability is presented. The buffer combines class-AB operation with rail-to-rail signal swing. A new adaptive biasing scheme is proposed with low complexity, thereby allowing the construction of a very compact, low-power analog voltage buffer with wide bandwidth and high slew rate. Simulated results using a 0.35-mum CMOS process are provided. The circuit operates from a single 1.5-V power supply and has a quiescent power consumption of only 282 muW.

Published in:

Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on

Date of Conference:

27-30 Aug. 2007

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