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In this paper, we show how novel recursive formulations of block pseudocirculant matrices lead to a new class of parallel cyclic convolution algorithms that exhibit a high degree of regularity and modularity and are suitable for parallel or pipelined implementation into today's very large scale integration (VLSI) circuits, multifield-programmable gate arrays (multi-FPGAs) systems, and multiprocessor architectures. In addition to the architectural advantages, the proposed formulations offer a comparable number of parallel subsections, and a reduction in the number of pre/postprocessing vector operations, for the same range of decimation rates proposed by the most efficient alternative algorithm. The proposed algorithms do not impose any of the traditional constraints, such as the demand that the convolution length be factorable into mutually prime factors. The use of recursion results in the definition of two new mathematical constructs, which are intrinsic to these novel architectures, the higher order block pseudocirculant or superblock pseudocirculant matrix and the block pseudocyclic shift operator that leads to unfolded data-flow graphs of cyclic shifts.