By Topic

Spice-accurate systemC macromodels of noisy on-chip communication channels

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Terrassan, N. ; ENDIF, Ferrara Univ., Ferrara ; Bertozzi, D. ; Bogliolo, A.

With the advent of nanoscale technologies, even RTL and system designers must consider interconnect analysis to provide predictable performance, reliability and meet power budgets. However, system-wide modeling of high-speed interconnects using conventional circuit simulators such as SPICE can become prohibitively CPU expensive. We propose to formulate analytical interconnect macromodels capturing noise effects, and to integrate them into the SystemC communication abstractions. Experimental results show that HDL simulations achieve an average accuracy of 5% from SPICE, while a few case studies illustrate the applicability of the proposed framework for fast exploration of physical channel configuration and performance estimation.

Published in:

Signal Propagation on Interconnects, 2007. SPI 2007. IEEE Workshop on

Date of Conference:

13-16 May 2007