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With the advent of nanoscale technologies, even RTL and system designers must consider interconnect analysis to provide predictable performance, reliability and meet power budgets. However, system-wide modeling of high-speed interconnects using conventional circuit simulators such as SPICE can become prohibitively CPU expensive. We propose to formulate analytical interconnect macromodels capturing noise effects, and to integrate them into the SystemC communication abstractions. Experimental results show that HDL simulations achieve an average accuracy of 5% from SPICE, while a few case studies illustrate the applicability of the proposed framework for fast exploration of physical channel configuration and performance estimation.